AL103 Revision 1.0
Table 5: MII Interface Port 4 (Continued)
M4RXCLK
M4RXER
M4CRS
113
112
101
103
I
I
I
I
Receive Clock.
Receive Data Error.
Carrier Sense.
M4COL
Collision Detect.
Table 6: MII Interface Port 5
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
M5TXD3
M5TXD2
M5TXD1
M5TXD0
131
132
133
135
O
Transmit Data - NRZ data to be transmitted to transceiver.
Signal TX_EN and TXD0 through TX_D3 are clocked out by
the rising edge of TX_CLK.
M5TXEN
136
O
I
Transmit Enable.
Synchronous to the transmit clock.
M5TXCLK
137
Transmit Clock Input.
25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
M5RXD3
M5RXD2
M5RXD1
M5RXD0
145
143
142
141
I
Receive Data - NRZ data from the transceiver.
For MII interface, signal RX_DV, RX_ER and RX_D0 through
RX_D3 are sampled by the rising edge of RX_CLK.
M5RXDV
M5RXCLK
M5RXER
M5CRS
140
139
138
123
125
I
I
I
I
I
Receive Data Valid.
Receive Clock.
Receive Data Error.
Carrier Sense.
M5COL
Collision Detect.
Table 7: MII Interface Port 6
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
M6TXD3
M6TXD2
M6TXD1
M6TXD0
152
153
154
156
O
Transmit Data - NRZ data to be transmitted to transceiver.
Signal TX_EN and TXD0 through TX_D3 are clocked out by
the rising edge of TX_CLK.
M6TXEN
157
O
Transmit Enable.
Synchronous to the transmit clock.
9/00
Reference Only / Allayer Communications
10
ABC [ ABC Taiwan Electronics Corp ]
