Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
V
OCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
12 V
V
S+
to V
S−
See Figure 3
V
S+
to V
S−
−65°C to +125°C
−40°C to +125°C
300°C
150°C
AD8137
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θ
JA
. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces the θ
JA
.
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W) and 8-lead LFCSP (θ
JA
= 70°C/W) on a JEDEC
standard 4-layer board. θ
JA
values are approximations.
3.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for the device soldered in a circuit board in still air.
Table 5. Thermal Resistance
Package Type
8-Lead SOIC/2-Layer
8-Lead SOIC/4-Layer
8-Lead LFCSP/4-Layer
θ
JA
157
125
70
θ
JC
56
56
56
Unit
°C/W
°C/W
°C/W
MAXIMUM POWER DISSIPATION (W)
2.5
LFCSP
2.0
1.5
1.0
SOIC-8
0.5
The maximum safe power dissipation in the
package
is limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the parametric
performance of the
Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
ESD CAUTION
Rev. E | Page 9 of 32
04771-0-022
MAXIMUM POWER DISSIPATION
AAVID [ AAVID THERMALLOY, LLC ]
