High Efficiency 1X/1.5X/2X Charge
Pump for White LED Applications
Since the input current sinks of the AAT3169 are
programmable, no PWM (pulse width modulation)
or additional control circuitry is needed to control
LED brightness. This feature greatly reduces the
burden on a microcontroller or system IC to man-
age LED or display brightness, allowing the user to
"set it and forget it." With its high-speed serial inter-
face (1MHz data rate), the input sink current of the
AAT3169 can be changed successively to brighten
or dim LEDs in smooth transitions (e.g., to fade-
out) or in abrupt steps, giving the user complete
programmability and real-time control of LED
brightness.
The 16 individual current level settings are each
approximately 1.8dB apart (see Table 1). Code 1 is
full scale; Code 15 is full scale attenuated by
approximately 25dB; and Code 16 is reserved as a
"no current" setting.
Data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AAT3169
AS
2
Cwire Serial Interface
The current sink input magnitude on the AAT3169
is controlled by AnalogicTech's Advanced Simple
Serial Control (AS
2
Cwire) serial digital input.
AS
2
Cwire adds addressing capability for multiple
data registers over the Simple Serial Control™
(S
2
Cwire™), which is only capable of controlling a
single register. The AAT3169 has four registers:
Bank1, Bank2, Max Current, and Low Current.
Three addresses are used to control the two regis-
ters. Address 0 addresses both registers simulta-
neously to allow the loading of both registers with
the same data using a single write protocol.
Address 1 addresses Register 1 for D1 to D5 cur-
rent level settings. Address 2 addresses Register 2
for D6 current level settings.
AS
2
Cwire relies on the number of rising edges of
the EN/SET pin to address and load the registers.
AS
2
Cwire latches data or address after the EN/SET
pin has been held high for time T
LAT
. Address or
data is differentiated by the number of EN/SET ris-
ing edges. Since the data registers are 4 bits each,
the differentiating number of pulses is 2
4
or 16, so
that Address 0 is signified by 17 rising edges,
Address 1 by 18 rising edges, and Address 2 by 19
rising edges. Data is set to any number of rising
edges between 1 and including 16. A typical write
protocol is a burst of EN/SET rising edges, signify-
ing a particular address, followed by a pause with
EN/SET held high for the T
LAT
timeout period, a
burst of rising edges signifying data, and a T
LAT
timeout for the data registers. Once an address is
set, then multiple writes consisting of data only
(without address) to the corresponding data regis-
ter are allowed. Address 0 is the default address
on the first rising edge after the AAT3169 has been
disabled. If data is presented on the first rising
edge with no prior address, both data registers are
simultaneously loaded.
Mean
30mA Max
30.0
29.3
27.8
25.2
22.8
20.9
18.5
16.1
13.7
10.0
9.4
7.0
4.7
3.3
1.9
0.0
Mean
20mA Max
20.0
19.5
18.5
17.5
15.4
14.2
12.5
10.9
9.3
8.0
6.5
4.9
3.3
2.4
1.5
0.0
Mean
15mA Max
15.0
14.6
13.9
12.7
11.5
10.5
9.3
8.1
7.0
6.0
4.9
3.7
2.6
1.9
1.2
0.0
Table 1: Mean Table of AAT3169 Output Current.
3169.2006.08.1.2
9
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
