A
i
4100
A/D Converter Output Code (Mode 1 Register D5=1)
The format of an ADC digital output is a straight binary.
When in the input zero reference voltage, the output code
will be all zero and when the input is a full scale voltage, the
output code will be all one
the ADCLK input after a 5.5 clock of pipeline delay.
High-Z Control of ADC Digital Output
ADC digital outputs become High-Z under the following
conditions
ㆍ
Set the ADC output bit to one. (Mode 1 register D2=1)
ㆍ
Set the STBY pin to low
ㆍ
Set the power control bit to one (Mode 1 register D0=1)
Clock, Pipeline Delay, Digital Data Output Timing
The ADCLK input is used for an A/D conversion. The ADC
input signal is sampled at the falling edge of the ADCLK
input and 10 bits parallel data is output at the rising edge of
Digital Output Code
A/D Input
MSB
D9
Full Scale
:
:
:
:
Zero Scale
1
:
1
0
:
0
D8
1
:
0
1
:
0
D7
1
:
0
1
:
0
D6
1
:
0
1
:
0
D5
1
:
0
1
:
0
D4
1
:
0
1
:
0
D3
1
:
0
1
:
0
D2
1
:
0
1
:
0
D1
1
:
0
1
:
0
LSB
D0
1
:
0
1
:
0
ADC Data Output (Coding : Straight Binary)
Miscellaneous Functions
(ADC Direct Input, ADIN Mode)
The direct input path to the ADC or the PGA is achieved by
means of a register setting. The selectable paths are as
follows:
ㆍFunction
disable (default, Mode 1 register D5=0, D4=0)
ㆍADIN
input to the PGA (Mode 1 register D5=0, D4=1)
ㆍADIN
input to the PGA (Mode 1 register D5=1, D4=Don’t
Care)
The BLK, SHD and SHP inputs are ignored at the ADIN
mode.
Polarity Inversion
The following input polarities can be inverted by register
setting:
ㆍADCLK
(A/D converter sampling clock, Mode 1 register
D6)
ㆍSHP
and SHD (CDS sampling clock, Mode 2 register D3
and D2)
ㆍBLK,
OBP, CCDCLP and ADCLP (Mode 2 register D3
and D2)
Data Output Clock
The ADCK input or the OUTCK input is selectable as an
ADC data output clock.
Power Down Mode
The power mode can be set either by register setting or by
the STBY pin.
Serial Interface Circuit
The internal registers of the Ai4110 are controlled by a 3-
wire serial interface. The data is a 16-bit length serial data
that consists of a 2-bit operation code, 4 bits address and
10bits data. Each bit is fetched at the rising edge of the CSN
input. Keep CSN to high when not access Ai4110. it is
prohibited to write to a non-defined address. When a data
length is below 16 bits, the data is not executed.
Monitor Output
When setting Mode 2 (D1 and D0), the signal from MONOUT
is selectable. The alternatives are OFF, CDS output, PGA
output or REFIN/CCDIN output. The MONOUT pin gain is
fixed to 0dB regardless of the gain control register setting
when the CDS output is selected. The MONOUT level
becomes V
COM
at zero reference level. The signals are
output in reverse for the CCD input
Registers
The Ai4100 has 10 bitsX7 registers that control the
operations. All registers are write only, the serial registers are
written by the serial interface.
8
A1PROS [ A1 PROS CO., LTD. ]
