V-Data
VDS8616A8A
Pin Description
PIN
NAME
FUNCTION
CK
System Clock
Active on the positive edge to sample all inputs.
CKE
Clock Enable
Chip Select
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Disables or Enables device operation by masking or enabling all input
except CK, CKE and L(U)DQM
A0~A12 Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A8
BS0~BS1 Banks Select
DQ0~DQ16 Data
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
/RAS
/CAS
/WE
Row Address Strobe
Column Address Strobe
Write Enable
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CK
Clock
Generator
Bank3
Bank2
CKE
Bank1
Address
Address
Buffer
&
Bank0
Mode
Register
Refresh
Counter
Amplifier
DQM
DQS
/CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
/RAS
/CAS
Data Control Circuit
DQ0~DQn
/WE
Rev 1.0 December, 2001
2
ADATA [ ADATA Technology Co., Ltd. ]
