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4
ISL40 SIGNALS
Device signals are defined in table 4.1.
Table 4.1 - Device signals
Configuration signals
F0F1-0
Control signals
HDO
CMOS
CMOS
CMOS
CMOS
O
I
20
28
24
33
32
36
21
CMOS+PD
CMOS+PD
CMOS+PD
CMOS+PD
CMOS+PD
CMOS+PD
CMOS+PD
CMOS+PD
I
I
I
I
I
I
I
I
42
43
nSleep
F0F1-1
INH
I
F0F1-2
34
35
45
46
4
Wake
I
F0F1-3
nReset
CMOS_Reset+PU I
BitRate0
BitRate1
Mode3 =1
Mode4 =1
InterfHop
Interfer
CMOS + PD
CMOS
I
O
Front-end signals
7
RxOn
DRxP
CMOS
CMOS
O
I
16
6
nExtendIn
AutoFreqCh
AutoSleep
Power signals
Vcc
CMOS+PD
CMOS+PD
CMOS+PD
I
I
I
40
26
27
DRxN
MF0nF1
TxOn
CMOS
CMOS
CMOS
I
5
41
14
13
1
O
O
Power
Power
Power
Power
Power
Power
P
P
P
P
P
P
48
3
Vcc
DTxO
Buf+Slew+3 State B
Gnd
12
19
OscIn
CMOS
CMOS
I
Gnd
OscOut
O
2
VccPLL
GndPLL
37
47
Sig I/O signals
SigIn0
CMOS+PD
I
38
SigIn1
SigIn2
SigIn3
SigIO4
SigIO5
SigIO6
SigIO7
SigO0
SigO1
SigO2
SigO3
ID0
CMOS+PD
CMOS
I
39
25
29
23
15
17
18
8
I
1
36
CMOS
I
OscOut
2
InterfHop
F0F1-3
F0F1-2
Wake
nReset
Id1
Id0
SigIn3
nSleep
AutoSleep
35
34
33
32
31
30
29
28
27
26
25
OscIn
3
BiDirectional+PD
BiDirectional+PD
BiDirectional+PD
BiDirectional+PD
CMOS
B
B
B
B
O
O
O
O
I
Vcc
4
Mode3
5
DRxN
6
DRxP
7
Mode4
8
ISL40
SigO0
9
SigO1
10
CMOS
9
SigO2
11
SigO3
12
Gnd
AutoFreqChange
SigIn2
CMOS
10
11
30
31
44
22
CMOS
CMOS+PD
CMOS+PD
CMOS+PD
CMOS+PD
ID1
I
ID2
I
ID3
I
Figure 4.1 - ISL40 Pinout
PD = internal pull down resistor
© 2007 Yamar Electronics Ltd.
7
DS-ISL40 R1.6
YAMAR [ YAMAR ELECTRONICS LTD. ]
