X24042
Sequential Read
Thedataoutputissequential,withthedatafromaddress
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
oneoperation. Attheendoftheaddressspace(address
511) the counter “rolls over” to address 0 and the
X24042 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowl-
edge and data transfer sequence.
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes; however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24042 continues to out-
put data for each acknowledge received. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
Figure 9. Sequential Read
S
SLAVE
ADDRESS
T
O
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
P
A
C
K
BUS ACTIVITY:
X24042
DATA n
DATA n+1
DATA n+2
DATA n+x
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Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
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8
XICOR [ XICOR INC. ]
