X24022
READ OPERATIONS
during the next eight clock cycles. The read operation is
terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
Figure 7 for the sequence of address, acknowledge and
data transfer.
Read operations are initiated in the same manner as
writeoperationswiththeexceptionthattheR/Wbitofthe
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.
Random Read
Randomreadoperationsallowthemastertoaccessany
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write operation. The mas-
ter issues the start condition, and the slave address
followed by the word address it is to read. After the word
addressacknowledge,themasterimmediatelyreissues
thestartconditionandtheslaveaddresswiththeR/W bit
set to one. This will be followed by an acknowledge from
the X24022 and then by the eight bit word. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
RefertoFigure8fortheaddress, acknowledgeanddata
transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
duringtheninthcycleorholdSDAHIGHduringtheninth
clock cycle and then issue a stop condition.
Current Address Read
Internally the X24022 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either
areadorwrite)wastoaddressn,thenextreadoperation
would access data from address n + 1. Upon receipt of
the slave address with R/W set to one, the X24022
issues an acknowledge and transmits the eight bit word
Figure 7. Current Address Read
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BUS ACTIVITY:
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SDA LINE
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Figure 8. Random Read
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SLAVE
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WORD
ADDRESS n
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
DATA n
SDA LINE
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