X1227
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
Watchdog Timer Control Bits—WD1, WD3
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
RTCF: Real Time Clock Fail Bit—Volatile
Watchdog Time-Out Period
WD1 WD3
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1227 inter-
nally) when the device powers up after having lost all
power to the device. The bit is set regardless of
0
0
1
1
0
1
0
1
1.75 seconds (Factory Default)
750 milliseconds
250 milliseconds
Disabled
whether V
or V
is applied first. The loss of only
CC
BACK
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR3 (Non-Volatile)
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
Block Protect Bits—BP2, BP1, BP3
A range from -30ppm to +30ppm can be represented
by using three bits above.
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array.The partitions are described in Table 3 .
Table 5. Digital Trimming Registers
DTR Register
Estimated frequency
DTR2
DTR1
DTR3
PPM
0 (Default)
+10
Table ±. Block Protect Bits
Protected Addresses
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
X1227
Array Lock
None
+20
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None (Default)
180 – 1FF
+30
Upper 1/4
h
h
h
h
0
100 – 1FF
h
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 pgs
-10
000 – 1FF
h
-20
000 – 03F
-30
h
h
h
000 – 07F
h
000 – 0FF
h
h
h
000 – 1FF
h
Characteristics subject to change without notice. 6 of 28
REV 1.1.20 1/13/03
www.xicor.com
XICOR [ XICOR INC. ]
