X1227
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
– *n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Bit
Reg
Name
Addr.
Type
Range
7
6
5
4
3
2
1
0 (optional)
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Status
RTC
(SRAM)
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
BL
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
BAT
0
0
Y23
0
0
MIL
0
0
0
0
AL1
0
0
Y22
0
0
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
RWEL
0
WEL
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
19/20
0-6
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
0-99
1-12
1-31
0-23
0-59
0-59
0
M22
S22
0
Control
(EEPROM)
0
ATR5
ATR4
ATR3
Unused
WD0
BP2
0
EDW1
BP1
0
0
BP0
WD1
0
0
DY2
0
0
DY1
0
00h
20h
00h
Alarm1
(EEPROM)
A1Y2K21 A1Y2K20 A1Y2K13
A1Y2K10
DY0
19/20
0-6
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0
0
0
A1M22
A1S22
0
EMO1
EDT1
EHR1
EMN1
ESC1
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
0
A1G11
A1D11
A1H11
A1M11
A1S11
0
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
1-12
1-31
0-23
0-59
0-59
19/20
0-6
00h
00h
00h
00h
00h
20h
00h
A1D21
A1H21
A1M21
A1S21
Alarm0
(EEPROM)
A0Y2K21 A0Y2K20 A0Y2K13
EDW0
0
0
0
0
DY2
DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0
0
EMO0
EDT0
EHR0
EMN0
ESC0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
A0D21
A0H21
A0M21
A0S21
0
A0M22
A0S22
Characteristics subject to change without notice. 4 of 28
REV 1.1.20 1/13/03
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XICOR [ XICOR INC. ]
