I5216 SERIES
Advanced Information
PRELIMINARY
I5216 CODEC DIAGRAM
µ/A-Law
Expander
or linear
14 bit
Digital
Smoothing
Interpolation Filter
0.8/1/1.2/1.25/1.4/1.6/1.8/2
14 bit
Digital
Σ∆
Demodulator
1 bit
1 bit D/A
&
SC
Filter
1
DAO
ANALOG OUT
3
(
ANALOG IN
LAW0
LAW1
)
2
(
MUTE
)
1
(DAPD)
(
COG0
COG1
COG2
)
Anti
Aliasing
Filter
SC
AMP
1
(
CIG0
CIG1
CIG2
)
(ADPD)
Analog
Σ∆
Modulator
1 bit
3
Digital
Anti-Aliasing
Decimation Filter
(
MUTE
)
1
15 bit
Digital
High pass
Filter
HPF0
HSR0
14 bit
Sample frequency
1
(
)
2
(
LAW0
LAW1
)
8 bits or 16
bits
(
I2S0
)
1
µ/A-Law
Compressor
or linear
(
HSR0
)
Digital
PLL
WS
PCM / I2S Interface
2
1
8 bits or 16
bits
(
CKD2
)
÷2
1
WS
SCK
SDIO
SDI
MCLK
5/8/01
-7
Publication Release Date: November 30, 2001
Revision A1
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