I5216 SERIES
Advanced Information
PRELIMINARY
BLOCK DIAGRAMS
I5216 Block Diagram
MICBS
MICROPHONE
2.2V Voltage
reference
1
(AGPD)
MIC+
MIC -
AGCCAP
MIC IN
INP
SUM1 MUX
AGC
1
Σ
)
2
SUM1
Summing
AMP
SUM1
ARRAY
SUM1
FILTO
AUX IN
2
Input Source MUX
(AGPD)
AUX IN
Auto mute
Auto gain
1
Low Pass
Filter
1
(
FILTO
S1M0
S1M1
Σ
SUM2
Summing
AMP
Filter
MUX
1
(FLS0)
(AMT0)
(FLPD)
(
S2M0
)
S2M1
1.0 / 1.4 / 2.0 / 2.8
SUM1 MUX
AUX IN
AUX IN
AMP
(INS0)
1
1
ARRAY
Internal
Clock
(AXPD)
DAO
2
(
AXG0
AXG1
)
(
(
OSPD
)
2
(
FLD0
)
CKDV
FLD1
SUM2
(ANALOG)
Multilevel
Storage Array
2
2
MCLK
MIC+
MIC-
÷2
1 (CKD2)
S1S0
S1S1
)
CTRL
(DIGITAL)
2 x 64 S/H
Array I/O Mux
Program/Read Control
FILTO
AUX
OUT
AMP
AUX OUT
Output MUX
A/D
2 x 64-bit reg.
SUM2
VOL
ARRAY OUT
(DIGITAL)
SPEAKER
Spkr.
AMP
ARRAY OUT
(ANALOG)
SP+
SP-
DAO
INP
SUM2
SUM1
2
CODEC
Mux
INP
DAO
SUM2
Volume
Control
1 (VLPD)
3
( )
CDI0
CDI1
2
( )
VOL0
VOL1
VOL2
(
OPS0
)
OPS1
2
Vol MUX
(
OPA0
)
OPA1
µ
-Law / A-Law /
Linear 14 bit
CODEC
2
(
VLS0
)
VLS1
(
ADPD
)
DAPD
2
Power Conditioning
PCM / I2S Interface
Device Control
V
CCA
V
SSA
V
SSA
V
SSD
V
SSD
V
CCD
V
CCD
WS
SCK
SDIO
SDI
SCL
SDA
INT
RAC
A0
A1
5/22/01
-6
Publication Release Date: November 30, 2001
Revision A1