87541V
Features
■
(Continued)
Universal
Synchronous/Asynchronous
Receiver-
Transmitter (USART)
—
Supports full-duplex USART communication
—
Has programmable baud rate
—
Supports polling and interrupt controlled data transfer
—
Supports synchronous mode with either internal or
external clock
—
Supports 9-bit Attention mode
Two 16-bit Multi-Function Timer (MFT16) modules;
each module:
—
Contains two 16-bit timers
—
Supports Pulse Width Modulation (PWM), Capture
and Counter
Timer and Watchdog (TWM)
—
16-bit periodic interrupt timer with 30
µs
resolution
and 5-bit prescaler for system tick and periodic
wake-up tasks
—
8-bit watchdog timer
Pulse Width Modulation (PWM) Module
—
Eight outputs
—
8-bit duty cycle resolution
—
8-bit common input clock prescaler
Analog to Digital Converter (ADC)
—
Five voltage channels (four external and one
internal), with 8-bit resolution
—
Sigma-delta technology for high noise rejection
—
Internal voltage reference
—
Every 100 ms, three of the five channels are measured
Digital to Analog Converter (DAC)
—
Four channels with 8-bit resolution
—
Rail-to-Rail output range, from AGND to AVCC
—
1
µs
conversion time
Host-Controlled Functions
■
Supports
Microsoft
®
Advanced Power Management
(APM) Specifications Revision 1.2,
February 1996
—
Generates the System Management Interrupt (SMI)
Supports
ACPI Specification Revision 2.0b,
July 27,
2000
—
Generates Power Management Interrupt (ECSCI)
—
Generates Power-Up Request (PWUREQ)
■
■
■
Host-controlled functions configuration PC01
—
PnP Configuration Register structure
—
Flexible resource allocation for all logical devices
❏
Relocatable base address
❏
■
15 IRQ routing options
■
Mobile System Wake-Up Control (MSWC)
—
Wake-up on detection of:
❏
External modem ring on RI
❏
❏
■
IRQ from Keyboard, Mouse and PM channels
Software-triggered event
—
Routing of wake-up to IRQ, SMI and PWUREQ
Miscellaneous Features
■
■
Clocks
—
Single 32.768 KHz crystal oscillator with buffered
output
—
LPC clock, 0 to 33 MHz
—
On-chip high frequency clock generator
❏
Provides core clock, 4-20 MHz
❏
❏
■
Software-controlled frequency generation
Generation is based on the 32.768 KHz clock
—
Buffered core clock output
■
Host-Core Interface Functions
■
Host Bus Interface (HBI)
—
Comprises three host interface ports, typically used
for KBC and ACPI EC channels:
❏
One 8042 KBC-standard, interface (legacy 60
16
,
64
16
).
❏
Strap Inputs for operation control
—
ENV1-0 for IRE/OBD/DEV operating mode selection
—
SHBM for shared BIOS control
—
TRI-STATE
®
for ISE/ADB support
Testability
—
TRI-STATE device pins, selected at power-up by
strap input
Power Supply
—
3.3V supply operation
—
5V tolerance and back-drive protection on all pins
(except LPC bus pins, keyboard scan inputs and
analog pins)
—
Separate supplies for Host-controlled functions
(V
DD
) and Core-controlled functions (V
CC
)
—
Pin for filtering the on-chip voltage regulator (V
CORF
)
—
Backup battery input for wake-up configuration
—
Four power modes, switched by software or
hardware with graduated current consumption
■
Two PM interface ports (legacy 62
16
, 66
16
and
68
16
, 6C
16
).
■
These provide ACPI Embedded Controller sup-
port with either “Shared” or “Private” interface
(regarding SCI/SMI generation).
—
Generates IRQ (with Legacy support), SMI and SCI
—
Provides Fast Gate A20 and Fast Keyboard Reset
via firmware
■
Core Access to Host-Controlled Functions
—
Host-Core arbitration of function control
—
Host access blocked by the core via lock bits
■
Package
—
176-pin LQFP package
Revision 1.0
3
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