87541V
Features
Embedded Controller
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Core-Controlled Functions
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CompactRISC CR16B Processing Unit - a 16-bit em-
bedded RISC processor core (the “core”)
Internal Memory
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Boot block for core code in 4 Kbytes of ROM
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2 Kbytes of on-chip RAM with contents protection
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ROM and RAM both can hold code and data
Bus Interface Unit (BIU) supporting:
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Up to 1 Mbyte for code and data
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Provides one chip-select for a flash/ROM device;
one additional chip-select is available in
Development mode for flash/ROM and SRAM
devices
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Provides one chip-select for I/O devices
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8- or 16-bit wide bus
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Configurable wait states
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Enhanced performance using fast read cycles
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Single-cycle, fast-read (word-aligned)
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Interrupt Control Unit (ICU)
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Non-maskable interrupt input (PFAIL)
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31 maskable vectored interrupts
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Enable and pending indication for each interrupt
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General-purpose external interrupt inputs through
MIWU
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Provides interrupt on system events (via MSWC)
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External modem ring on RI
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IRQ from Keyboard, Mouse and PM channels
Software-triggered event
System ACPI sleep-state change
Power Button mode change
Legacy software “Off” command
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Two-byte, burst-read (byte-aligned)
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BIOS sharing with PC host
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Host-core shared memory access protection
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Host-controlled with core override
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Multi-Input Wake-Up (MIWU)
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Supports up to 20 wake-up inputs
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Provides user-selectable trigger conditions
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Provides wake-up on activity of external pins
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General-purpose wake-up inputs
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Power switch input
Keyboard scan inputs
64-Kbyte and 8-Kbyte blocks with independent
protection
Hardware-protected boot zone for host code
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Generates wake-up event to Power Management
Controller (PMC)
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Generates interrupts to ICU
General-Purpose I/O (GPIO)
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88 port pins (including keyboard scanning)
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I/O pins individually configured as input or output
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Optional internal pull-up resistors on inputs
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Special ports for internal keyboard matrix scanning
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16 open-collector outputs
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Download for on-board code updating
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Host-controlled via LPC
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Core-controlled via JTAG or serial port
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External memory “power-down” mode
Operation Modes
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IRE - Normal operation mode
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OBD - On-Board Development mode
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Used for development in the final system
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Eight Schmitt inputs with internal pull-ups
Communicates with debugger via JTAG interface
Supports hardware breakpoint
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Dedicated input for system On/Off switch
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External GPIO expansion through the
BIU I/O Expansion protocol
Three PS/2 Interfaces
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Supports external ports for: external keyboard,
mouse and an additional pointing device
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Supports byte-level handling via hardware
accelerator
Two ACB Interface modules. Each module:
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Is Intel SMBus and Philips I
2
C
®
compatible
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Is SMBus master and slave
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Detects four simultaneous slave addresses (two
user-defined, broadcast and ARP)
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Supports polling and interrupt controlled operation
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Generates a wake-up event on detection of a Start
Condition (while in Idle mode)
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Has an optional internal pull-up on SDA and SCL pins
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DEV - Development mode
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Used in In-System Emulators (ISE) and Applica-
tion Development Boards (ADB)
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Communicates with debugger via JTAG interface
On-chip ROM is replaced with off-chip SRAM
Cycle-by-cycle compatible with IRE mode
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LPC System Interface
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8-bit I/O and 8-bit memory read and write cycles
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8-bit Firmware Memory read and write with wait-
sync cycles
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Bootable memory support
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Base Address (BADDR) strap to determine the base
address of the Index-Data register pair
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Serial IRQ (SERIRQ) support
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LPCPD and CLKRUN support
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