W78E516B
5. BLOCK DIAGRAM
P1.0
Port
1
Port 1
Latch
ACC
Interrupt
T1
Timer
2
Timer
0
Timer
1
UART
PSW
ALU
Stack
Pointer
T2
P1.7
B
Port 0
Latch
Port
0
P0.0
P0.7
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
P3.0
Port
3
Port 3
Latch
Instruction
Decoder
&
Sequencer
SFR RAM
Address
64KB
APROM
4KB
LDROM
P3.7
512 bytes
RAM & SFR
P2.0
Port 2
Latch
Port
2
Bus & Clock
Controller
P2.7
P4.0
P4.3
Port
4
Port 4
Latch
Oscillator
Reset Block
Power control
XTAL1
XTAL2
ALE
PSEN
RST
VCC
Vss
6. FUNCTIONAL DESCRIPTION
The W78E516B architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port and an internal 74373 latch and 74244 buffer which can be switched to
port2. The processor supports 111 different opcodes and references both a 64K program address
space and a 64K data storage space.
6.1 RAM
The internal data RAM in the W78E516B is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
•
RAM 0H
−
7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
•
RAM 80H
−
FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
R1 of the selected registers bank.
-6-
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