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WCMA2016U4B-FF70 参数 Datasheet PDF下载

WCMA2016U4B-FF70图片预览
型号: WCMA2016U4B-FF70
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×16静态RAM [128K x 16 Static RAM]
分类和应用:
文件页数/大小: 12 页 / 239 K
品牌: WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
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WCMA2016U4B
Switching Characteristics
Over the Operating Range
[8]
55ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[10]
t
HZBE
WRITE CYCLE
[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9, 11]
WE HIGH to Low Z
[9]
5
55
45
45
0
0
40
50
25
0
20
10
70
60
60
0
0
50
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[9]
OE HIGH to High Z
[9, 11]
CE LOW to Low Z
[9]
CE HIGH to High Z
[9, 11]
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
[9]
BHE / BLE HIGH to High Z
[9, 11]
5
25
0
55
55
5
25
10
25
0
70
70
5
25
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min
Max
Min
70 ns
Max
Unit
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of
the specified I
OL
/I
O H
and 30 pF load capacitance.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for
any given device.
10. If both byte enables are toggled together this value is 10ns
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured
when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write..
5