WCMA1008C1X
Switching Characteristics
Over the Operating Range
55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write
End
Address Set-Up to Write
Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
55
45
45
0
0
45
25
0
5
20
70
60
60
0
0
50
30
0
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address
Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
CE
1
HIGH to High Z, CE
2
LOW to High Z
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
CE
1
HIGH to Power-Down,
CE
2
LOW to Power-Down
0
55
5
20
0
70
0
20
5
25
5
55
20
0
25
55
55
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
70
Max.
Unit
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified I
OL
/I
OH
and 100-pF load capacitance.
5. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE
1
LOW and CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate
a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
Page 4 of 11
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
