VG36256401A
VG36256801A
Preliminary
VG36256161A
CMOS Synchronous Dynamic RAM
VIS
A.C Characteristics : (Ta = 0 to 70°C V
= 3.3V±0.3V, V = 0V)
DD
SS
symbol
A.C. Parameter
-75
Min.
-8H
unit
note
Max.
Min.
Max.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Row cycle time
RAS to CAS delay
60
70
RC
20
20
20
20
50
10
10
3
RCD
RP
ns
Precharge to refresh/row activate command
Row activate to row activate delay
Row activate to precharge time
CL2
15
15
RRD
RAS
CK2
CK3
CH
37.5
7.5
100,000
100,000
Clock cycle time
CL3
7.5
Clock high time
Clock low time
2.25
2.25
3
CL
ns
Access time from CLK
(positive edge)
CL2
CL3
4
4
6
6
AC2
AC3
T
Transition time of CLK (Rise and Fall)
CAS to CAS Delay time
1
1
2
0
10
1
1
3
0
10
CLK
CCD
OH
Data output hold time
Data output low impedance
LZ
CL2
CL3
4
4
6
6
HZ2
HZ3
IS
ns
Data output high impedance
9
Data/Address/Control Input setup time
Data/Address/Control Input hold time
1
0.5
1
2
1
1
2
2
1
IH
Minimum CKE ”High”for Self-Refresh exit
Power Down Exit set-up time
Mode Register Set Cycle
CLK
ns
SRX
PDE
RSC
DPL
DAL2
DAL3
BDL
REF
2
2
CLK
CLK
Data-in to precharge
2
Data-in to ACT (REF) Command
CL2
CL3
2clk+t
2clk+t
1
1clk+t
1clk+t
1
RP
RP
RP
RP
ns
Last data in to burst stop
CLK
ms
64
64
Refresh time (8,192 refresh cycles)
Document : 1G5-0155
Rev.1
Page 7
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
