VG36128401A
VG36128801A
Preliminary
VG36128161A
CMOS Synchronous Dynamic RAM
VIS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
-75
-8H
Unit Notes
Parameter
Symbol
ICC1
Test Conditions
Burst length = 1
One bank active
tRC ³ tRC(MIN.), Io = 0mA
Min
Max
Min
Max
x4
x 8
x16
120
125
135
2
100
105
115
2
mA
1
Operating current
Precharge standby
current in Power
down mode
Precharge standby
current in Nonpower
down mode
ICC2P
ICC2PS
ICC2N
mA
mA
CKE £ VIL(MAX.) CK
t
= min.
2
2
¥
CKE £ VIL(MAX.) CK
t
=
20
20
³
CKE VIH(MIN.) CK
t
= min.
³
CS VIH(MIN.)
Input signals are changed one
time during 2 CLK cycles.
ICC2NS
7
7
³
¥
CKE VIH(MIN.) CK =
t
CLK £ VIL(MAX.)
Input signals are stable.
Active standby current ICC3P
7
5
7
5
mA
mA
CKE £ VIL(MAX.) CK
t
= min.
in Power
down mode
ICC3PS
¥
CKE £ VIL(MAX.) CK
t
=
Active standby
current in Nonpower
down mode
ICC3N
30
30
³
CKE VIH(MIN.) CK
t
= min.
³
CS VIH(MIN.)
Input signals are changed one
time during 2CLKs
ICC3NS
20
20
³
¥
CKE VIH(MIN.) CK =
t
CLK £ VIL(MAX.)
Input signals are stable.
Operating current
(Burst mode)
ICC4
x4
x 8
x16
115
130
160
190
105
120
150
190
³
tCK tCK(MIN.) Io = 0mA
mA
2
3
All banks Active
Refresh current
ICC5
ICC6
tRC = 4 x tRC(MIN)
mA
mA
Self refresh Current
1
1
1
1
CKE£ 0.2V
Input Ieakage current
(Inputs)
lLI
-1
-1
uA
£
³
VIN 0, VIN VDD(MAX.)
Pins not under test = 0V
Intput leakage current
(I/O pins)
lLO
-1.5
1.5
0.4
-1.5
1.5
0.4
uA
£
³
VOUT 0, VOUT VDD(MAX.)
DQ# in H - Z., Dout Disabled
Output Low Voltage
Output High Voltage
VOL IOL = 2mA
VOH IOH = -2mA
V
V
4
4
2.4
2.4
Notes : 1. I
depends on output loading and cycle rates. Specified values are obtained with the output open.
CC1
In addition to this, I
is measured on condition that addresses are changed only one time during t
.
CC1
CK(MIN.)
2. I
depends on output loading and cycle rates. Specified values are obtained with the output open.
CC4
In addition to this, I
is measured on condition that addresses are changed only one time during t
.
CK(MIN.)
CC4
3. I
is measured on condition that addresses are changed only one time during t
.
CK(MIN.)
CC5
4. For LVTTL compatible.
Document : 1G5-0154
Rev.1
Page 5
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
