VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
VIS
DC Characteristics ; 3.3 - Volt Version
(T = 0 to 70°C, VCC = + 3.3V ±10 %, V = 0V)
a
SS
Parameter
Symbol
Test Conditions
VG26(V)(S)18165C
-5 -6
Min Max Min Max
Unit Notes
Operating current
Low
ICC1
RAS cycling
LCAS / UCAS cycling
tRC = min
-
-
-
120
-
-
-
110
mA
mA
mA
1, 2
ICC2
LVTTL interface
RAS, LCAS / UCAS = VIH
0.5
0.5
power
S-version
Dout = High-Z
CMOS interface
0.15
0.15
RAS, CAS ³ VCC -0.2V
Dout = High-Z
Standby
Current
Standard
power
LVTTL interface
RAS, LCAS / UCAS = VIH
-
-
2
-
-
2
mA
mA
version
Dout = High-Z
CMOS interface
RAS,CAS ³ VCC -0.2V
Dout = High-Z
0.5
0.5
RAS- only refresh current
EDO page mode current
ICC3
RAS cycling
LCAS / UCAS = VIH
-
120
-
110
mA
1, 2
tRC = min
ICC4
ICC5
tPC = min
-
-
90
-
-
80
mA
mA
1, 3
1, 2
CAS- before- RAS refresh
current
tRC = min
120
110
RAS, LCAS / UCAS cycling
Self- refresh current
(S-Version)
ICC8
ICC9
-
-
250
300
-
-
250
300
tRASS ³ 100ms
mA
mA
CAS- before- RAS long
refresh current
(S-Version)
Standby: VCC-0.2V £ RAS
CAS before RAS refresh:
2048 cycles / 128ms
RAS, LCAS / UCAS :
0V £ VIL £ 0.2V
VCC-0.2V £ VIH £ VIH (max)
Dout = High-Z, tRAS £ 300ns
Document:1G5-0147
Rev.1
Page8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
