VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
VIS
DC Characteristics; 5- Volt Verion
(T = 0 to + 70 °C, VCC= + 5V ±10 %,V = 0V)
a
SS
Parameter
Symbol
Test Conditions
VG26(V)(S)18165C
-5 -6
Min Max Min Max
Unit Notes
Operating current
ICC1
RAS cycling
LCAS / UCAS cycling
tRC = min
-
-
-
120
-
-
-
110
mA
mA
mA
1, 2
Low
power
S-version
TTL interface
RAS, LCAS / UCAS = VIH
2
2
Dout = High-Z
CMOS interface
0.25
0.25
RAS,CAS ³ Vcc -0.2V
Dout = High-Z
Standby
Current
ICC2
Standard
power
TTL interface
RAS,LCAS / UCAS = VIH
2
1
-
-
2
1
mA
mA
version
Dout = High-Z
CMOS interface
RAS, CAS ³ Vcc -0.2V
Dout = High-Z
RAS-only
ICC3
RAS cycling,
-
120
-
110
mA
1, 2
refresh current
LCAS / UCAS = VIH
tRC = min
EDO page mode
current
ICC4
tRC = min
-
-
90
-
-
80
mA
mA
1, 3
1, 2
CAS-before-RAS
refresh current
ICC5
tRC = min
120
110
RAS, LCAS / UCAS cycling
Self-refresh current
(S - Version)
ICC8
-
-
350
500
-
-
350
500
tRAS ³ 100ms
mA
mA
CAS- before- RAS long
refresh current
(S-Version)
ICC9
Standby: VCC-0.2V £ RAS
CAS before RAS refresh:
2048 cycles / 128ms
RAS,LCAS / UCAS:
0V £ VIL £ 0.2V
VCC-0.2V £ VIH £ VIH (Max)
Dout = High-Z, tRAS £ 300ns
Document:1G5-0147
Rev.1
Page6