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10-FZ062TA099FH-P980D18 参数 Datasheet PDF下载

10-FZ062TA099FH-P980D18图片预览
型号: 10-FZ062TA099FH-P980D18
PDF下载: 下载PDF文件 查看货源
内容描述: [Vincotech clip-in housing]
分类和应用:
文件页数/大小: 20 页 / 871 K
品牌: VINCOTECH [ VINCOTECH ]
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10-FZ062TA099FH-P980D18/-FH01-P980D28  
datasheet  
Characteristic Values  
Conditions  
Value  
Typ  
Parameter  
Symbol  
Unit  
V r [V] or I C [A] or  
V GE [V] or  
V GS [V]  
V CE [V] or I F [A] or  
T j  
Min  
Max  
V DS [V]  
I D [A]  
Input Rectifier Diode  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=150°C  
1,16  
1,11  
0,9  
0,77  
9
1,4  
V F  
V to  
r t  
30  
30  
30  
V
V
Forward voltage  
Threshold voltage (for power loss calc. only)  
Slope resistance (for power loss calc. only)  
Reverse current  
mΩ  
mA  
12  
0,02  
2
I r  
1500  
Thermal grease  
R th(j-s) thickness≤50um  
1,72  
K/W  
Thermal resistance chip to heatsink  
λ =1 W/mK  
Input Rectifier Thyristor  
Forward voltage  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
1,25  
1,22  
0,93  
0,82  
0,011  
0,014  
1,6  
V F  
V to  
r t  
30  
30  
30  
V
V
Threshold voltage (for power loss calc. only)  
Slope resistance (for power loss calc. only)  
Reverse current  
mΩ  
mA  
µs  
0,05  
2
2
I r  
800  
Ig=0,5A  
dig/dt=0,5A/us  
Ig=0,2A  
dig/dt=0,2A/us  
t GD  
VD=1/2Vdrm  
Gate controlled delay time  
Gate controlled rise time  
Critical rate of rise of off-state voltage  
Critical rate of rise of on-state current  
Circuit commutated turn-off time  
Holding current  
Tj=25°C  
Tj=125°C  
Tj=125°C  
Tj=125°C  
Tj=25°C  
Tj=25°C  
<1  
t GR  
µs  
500  
150  
(dv /dt )cr  
VD=2/3Vdrm  
V/µs  
A/µs  
µs  
Ig=0,2A  
f=50Hz  
VD=2/3Vdrm  
tp=200us  
(di /dt )cr  
VD=2/3Vdrm40  
150  
t q  
100  
26  
VD=6V  
50  
90  
I H  
mA  
mA  
V
tp=10us  
Ig=0,2A  
VD=6V  
I L  
Latching current  
Tj=25°C  
Tj=-40°C  
Tj=25°C  
Tj=-40°C  
Tj=125°C  
1,3  
1,6  
28  
50  
0,2  
V GT  
Gate trigger voltage  
VD=6V  
11  
I GT  
mA  
V
Gate trigger current  
V GD  
VD=1/2Vdrm  
VD=1/2Vdrm  
Gate non-trigger voltage  
Gate non-trigger current  
Tj=125°C  
1
I GD  
mA  
Thermal grease  
thickness≤50um  
λ = 1 W/mK  
R th(j-s)  
K/W  
1,57  
Thermal resistance chip to heatsink  
PFC MOSFET  
V (BR)DS  
r DS(on)  
V (GS)th  
I GSS  
I DSS  
t d(on)  
t r  
Avalanche breakdown voltage  
Static drain to source ON resistance  
Gate threshold voltage  
Gate to Source Leakage Current  
Zero Gate Voltage Drain Current  
Turn On Delay Time  
Rise Time  
0
0,0003  
Tj=25°C  
600  
2,5  
V
mΩ  
V
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
Tj=25°C  
Tj=125°C  
111  
223  
3,0  
10  
Vds  
20  
0
18  
3,9  
200  
10  
0,0012  
0
nA  
uA  
600  
21  
21  
4
4
71  
73  
3
3
0,055  
0,059  
0,008  
0,013  
ns  
t d(off)  
t f  
Turn off delay time  
Rgoff=4 Ω  
Rgon=4 Ω  
10  
400  
15  
Fall time  
E on  
Turn-on energy loss  
Turn-off energy loss  
Total gate charge  
mWs  
nC  
E off  
Q GE  
Q GS  
60  
0
0
400  
100  
18  
14  
Gate to source charge  
Gate to drain charge  
Input capacitance  
Q GD  
C iss  
20  
2800  
130  
2,5  
C oss  
C rss  
f=1MHz  
Tj=25°C  
pF  
Output capacitance  
Reverse transfer capacitance  
Thermal grease  
R th(j-s) thickness≤50um  
1,13  
K/W  
Thermal resistance chip to heatsink  
λ = 1 W/mK  
copyright Vincotech  
3
10 Febr. 2015 / Revision 4