CD54HC194, CD74HC194, CD74HCT194
Functional Diagram
3
4
5
6
15
14
13
12
D
D
D
D
Q
Q
Q
Q
0
1
2
3
0
1
2
3
7
2
9
10
1
11
GND = 8
= 16
DSL
DSR
S0
V
CC
S1
MR
CP
TRUTH TABLE
INPUTS
OUTPUT
OPERATING
MODE
Reset (Clear)
Hold (Do Nothing)
Shift Left
CP
X
X
↑
MR
L
S1
S0
X
l
DSR
DSL
X
D
Q
Q
Q
Q
n
0
1
2
3
X
l
X
X
X
X
l
X
L
L
L
L
H
X
X
X
X
X
X
q
q
q
q
q
q
q
q
d
q
q
q
q
q
d
q
0
1
1
1
2
2
0
0
1
2
3
3
1
1
2
3
H
h
h
l
l
l
L
↑
H
l
h
H
Shift Right
↑
H
h
h
h
X
L
q
2
2
3
↑
H
l
h
X
X
H
q
d
Parallel Load
↑
H
h
X
d
d
0
n
H = High Voltage Level,
h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition,
L = Low Voltage Level,
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition,
d
(q ) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock
n
n
Transition,
X = Don’t Care,
↑ = Transition from Low to High Level
2