Test Circuits and Waveforms
t
t
f
r
INPUT LEVEL
CP
90%
MR
INPUT LEVEL
GND
V
10%
S
V
S
V
10%
S
V
V
S
S
t
GND
t
W
t
W
PLH
t
REM
INPUT LEVEL
GND
V
t
PHL
S
CP
Q
Q
t
PHL
90%
S
10%
V
V
S
V
S
t
t
TLH
THL
FIGURE 1. CLOCK PREREQUISITE TIMES AND
FIGURE 2. MASTER RESET PREREQUISITE TIMES AND
PROPAGATION DELAYS
PROPAGATION AND OUTPUT TRANSITION TIMES
VALID
VALID
S OR DS
INPUT LEVEL
INPUT LEVEL
V
S
DATA
CP
V
S
GND
GND
t
t
SU
H
t
SU
t
H
INPUT LEVEL
INPUT LEVEL
V
S
V
S
CP
GND
GND
FIGURE 3. DATA PREREQUISITE TIMES
FIGURE 4. PARALLEL LOAD OR SHIFT-LEFT/SHIFT-RIGHT
PREREQUISITE TIMES
7