Handshake Control of Data Transfer
the processor, which then reads the data, causing generation
The
allows positive control of data transfer
processor and peripheral devices
lines
handshake data on both a read and a write
of a “Data Taken”
The peripheral device
This process continues
between the
by making new data
until the data transfer is
through the Operation of “handshake” lines. Port
A
Operation while the Port
on a write Operation only.
B
lines
handshake
In the
“Read” Handshaking is
possible on the Peripheral A port
input pin accepts the “Data Ready”
The CA1 interrupt
and CA2
generates the “Data Taken”
will set an internal
The “Data Ready”
which may interrupt the
control.
Read Handshake
Positive control of data transfer from peripheral devices
into the processor be accomplished very
processor or which may be
‘The “Data Taken” Signal
either be a pulse or a
processor and is cleared
These Options are shown
tively using Read Handshaking. In this
device must generate the equivalent of
the peripheral
“Data Ready”
which is set
by the
a
by the “Data Ready”
to the processor signifying that valid data is present
in Figure 12 which illustrates the normal Read Handshaking
This
interrupts
on the peripheral
REG
REG 1
OUTPUT REGISTER
OR
INPUT REGISTER
MPU
PA
MPU
Level
Output
MPU
On
Output
MPU
the
the
IRA bit which is
(OUTPUT)
of the PA
of last CA1
transition.
at
(Input
no effect
MPU reads
MPU
PA
bit which is
ORA.
no
(INPUT)
the
of the PA pin at
the time of the last CA1
transition
DORA
Figure 10. Output Register A
Input Register A
Input Register B
Figure 9. Output Register B
REG 2
AND REG 3
“0” ASSOCIATED
(HIGH-IMPEDANCE)
PIN AN INPUT
1
AN OUTPUT
DETERMINED BY
ASSOCIATED
WHOSE LEVEL
PIN
Figure 11. Data
Registers
Write Handshake
similar to that described for Read Handshaking. However,
for Write Handshaking, the generates the “Data
The
of operations which allows handshaking data
processor to a peripheral device is very
from the
5 - 2 6
UMC [ UMC CORPORATION ]
