Pin Description
RES
register are
into the processor.
are high-impedance inputs and data
the processor into the selected register.
is unselected, the data bus lines are
on the data bus lines and transferred
write cycles, these lines
transferred from
When the
The reset input clears
(except Tl and T2
Register). This
internal registers to logic “0”
and counters and the Shift
lines in the
all
input state, disables the timers, shift register, etc. and
disables interrupting from the
impedance.
CS2 (Chip
(Input
The two
select inputs are normally connected to
The input clock is the
trigger all data transfers between the
the
clock and is used to
processor and
processor address lines either directly or through
The selected
register will be accessed when
CS1 is high and CS2 is low.
RSO- RS3 (Register Selects)
The
of the data transfers between the
processor is by the
The four Register Select inputs permit the
to select one of the 16 internal registers of the
as shown in Figure 6.
processor
and the
Iine.
is low, data will be transferred out of the processor
into the selected
is high and the
out of the
register (write Operation). If
is selected, data will be transferred
(read Operation).
(Interrupt
The Interrupt Request output goes low whenever an
internal interrupt flag is set and the corresponding interrupt
enable bit is a logic “1”. This output is “opendrain” to
DBO-DB7 (Data Bus)
The eight bi-directional data bus lines are used to transfer
data between the and the processor.
the interrupt request
other equivalent in the
to be
with
read cycles, the contents of the selected
RS Coding
Description
Register
Register
Desig.
Number
RS3
RS2
0
RSO
Write
Read
0
0
0
0
Output Register “B”
Output Register
“ B ”
Input Register “A”
1
0
0
0
1
1
15
1
1
Same as
1 Except No. “Handshake”
Figure 6.
Internal Register Summary
5 - 2 4
.
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