THCV213-214_Rev.2.40_E
PIN Description
THCV213 Pin Description
PIN Name
PIN No
Type
Description
TXOUT1-,TXOUT1+ 20, 19
TXOUT2-,TXOUT2+ 16, 15
LVDSOUT LVDS output.
LVDSOUT LVDS output for Dual Display mode.
Identical to TXOUT1+/-.
Hi-Z when Normal operation.
D0-D17
32, 33, 34, 35, IN
Data input.
37, 38, 39, 40,
41, 43, 44, 45,
46, 47, 1, 2, 3, 4
27, 28, 29
Active if input DE=High
SYNC2-SYNC0
IN
Sync input.
Active if input DE =Low.
Input sync data pulse must be wider than or equal to
two input clock periods.
Data Enable (DE) input.
Refer to Table2 for requirements.
Clock input.
DE
30
6
IN
IN
IN
CLKIN
PDWN
5 MHz to 40MHz.
H: Normal operation.
10
L: Power Down, TXOUT1+/-, (TXOUT2+/-) are
Hi-Z.
EDGE
23
IN
IN
Input clock triggering edge select.
H: Rise edge, L: Fall edge.
Select the level of pre-emphasis.
PRE0, PRE1
11, 12
PRE1
PRE0
Description
L
L
H
H
L
H
L
w/o Pre-Emphasis
w/ 25% Pre-Emphasis
w/ 50% Pre-Emphasis
w/ 100% Pre-Emphasis
H
INIT
25
9
IN
IN
IN
H: Triggers SYNC pattern output fromTXOUT1+/-
and (TXOUT2+/-), normally used in Shake
Hand mode.
L: Normal operation.
H: Dual Display mode
DUAL
PRBS
Both TXOUT1+/- and TXOUT2+/- enabled.
L: Normal operation
Only TXOUT1+/- enabled.
8
H: Internal test pattern generator is enabled.
Pseudo-Random Bit Sequence (PRBS) is
generated and is fed into input data latches.
Normally used for debug.
L: Normal operation.
VDD
GND
LVDSVDD
LVDSGND
PLLVDD
PLLGND
7, 26, 36, 48
5, 22, 24, 31, 42
17
18, 21
13
Power
Power
Power
Power
Power
Power
Power supply pins for digital circuitry.
Ground pins for digital circuitry.
Power supply pin for LVDS output.
Ground pins for LVDS output.
Power supply pin for PLL circuitry.
Ground pin for PLL circuitry.
14
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THine Electronics, Inc.
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