THC63LVDR84C_Rev.1.20_E
Switching Characteristics
Over recommended operating supply and temperature range unless otherwise specified
Symbol
tRCP
tRCH
tRCL
tRCD
Parameter
RCLK and CLKOUT Transition Time
LVCMOS CLKOUT High Time
LVCMOS CLKOUT Low Time
RCLK IN to CLKOUT Delay
Min
8.92
-
-
Typ*
T
T/2
Max
125
-
-
-
Unit
ns
ns
ns
T/2
(3/14+3)×T
-
ns
tRS
tRH
tTLH
tTHL
LVCMOS Data Setup to CLKOUT
LVCMOS Data Hold from CLKOUT
LVCMOS Low to High Transition Time
LVCMOS High to Low Transition Time
0.35×T - 0.3
0.45×T - 1.6
-
-
-
-
-
ns
ns
ns
ns
0.7
0.7
-
1.0
1.0
0.55
0.25
-
PCLK=65MHz
PCLK=112MHz
-0.55
-0.25
tSK
LVDS Receiver Skew Margin
ns
-
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
tRPLL
LVDS Input Data Position0
LVDS Input Data Position1
LVDS Input Data Position2
LVDS Input Data Position3
LVDS Input Data Position4
LVDS Input Data Position5
LVDS Input Data Position6
Phase Lock Loop Set
- tSK
0.0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
-
+ tSK
ns
ns
ns
ns
ns
ns
ns
ms
T/7- tSK
2T/7- tSK
3T/7- tSK
4T/7- tSK
5T/7- tSK
6T/7- tSK
-
T/7+ tSK
2T/7+ tSK
3T/7+ tSK
4T/7+ tSK
5T/7+ tSK
6T/7+ tSK
10.0
*Typ values are at the conditions of VCC33=3.3V and Ta = +25ºC
Table 8. LVCMOS & LVDS Receiver AC Specifications
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