THC63LVDR84C_Rev.1.20_E
Equivalent LVDS Input Schematic Diagram
Output
Control
LVDS VCC
LVDS VCC
CMP
LVDS VCC
LVDS +
LVDS -
AMP
Figure 3. LVDS Input Schematic Diagram
Output Control
/PDWN
RCLK +/- Input
Valid Clock
Invalid Clock
Open or Hi-z
Don’t Care
LVCMOS Output
Active Clock & Data
Unfixed Clock & Data
All Low
H
H
H
L
All Low
Table 4. LVCMOS Output Data Control
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