THC63LVD823B_Rev.3.1_E
Pin Description (Continued)
Pin Name
Pin #
Type
Description
Output enable.
O/E
17
IN
H: Output enable,
L: Output disable (all outputs are Hi-Z).
H: Normal operation,
/PDWN
19
20
IN
IN
L: Power down (all outputs are Hi-Z)
PRBS (Pseudo-Random Binary Sequence) generator is
active in order to evaluate eye patterns when
a
MODE<1:0> = LL (Dual-in/Dual-out mode).
H: PRBS generator is enable.
PRBS
L: Normal Operation
Reserved
DDRN
21
13
IN
IN
Must be tied to GND.
DDR function is active when
MODE<1:0> = HL (Single-in/Dual-out mode).
Open or H: DDR (Double Edge input) function disable.
L: DDR (Double Edge input) function enable.
Must be Open.
N/C
22
3, 55, 71, 87
4, 18, 56,
72, 88
VCC
Power
Power Supply Pins for TTL inputs and digital circuitry.
GND
Ground
Ground Pins for TTL inputs and digital circuitry.
LVCC
LGND
PVCC
PGND
33, 45
Power
Ground
Power
Power Supply Pins for LVDS Outputs.
Ground Pins for LVDS Outputs.
Power Supply Pin for PLL circuitry.
Ground Pins for PLL circuitry.
26, 38, 50
24
23, 25
Ground
a: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of
23-1. The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and serialized
2
into TXOUT output. This function is normally to be used for analyzing the signal integrity of the transmission
channel including PCB traces, connectors, and cables.
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
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