THC63LVD823B_Rev.3.1_E
Pin Description
Pin Name
TA1+, TA1-
Pin #
48, 49
46, 47
43, 44
39, 40
41, 42
36, 37
34, 35
31, 32
27, 28
Type
Description
TB1+, TB1-
TC1+, TC1-
TD1+, TD1-
TCLK1+, TCLK1-
TA2+, TA2-
The 1st Link.
The 1st pixel output data when Dual-Link.
LVDS OUT
LVDS OUT LVDS Clock Out for 1st and 2nd Link.
TB2+, TB2-
TC2+, TC2-
TD2+, TD2-
The 2nd Link.
LVDS OUT
These pins are disabled when Single Link.
Additional LVDS Clock Out. Identical to TCLK1+,-.
TCLK2+, TCLK2-
29, 30
LVDS OUT
No connect if not used.
R17 ~ R10
G17 ~ G10
B17 ~ B10
R27 ~ R20
G27 ~ G20
60 -57, 54 - 51
68 - 61
IN
IN
The 1st Pixel Data Inputs.
The 2nd Pixel Data Inputs.
78 - 73, 70, 69
86 - 79
96 - 89
6, 5, 2, 1,
B27 ~ B20
100 - 97
DE
9
8
IN
IN
IN
IN
Data Enable Input.
Vsync Input.
VSYNC
HSYNC
CLKIN
7
Hsync Input.
10
Clock Input.
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
R/F
11
IN
LVDS swing mode, V
select. See Fig4 - 5.
REF
LVDS
Swing
Small Swing
Input Support
RS
VIHM
VIMM
VILM
350mV
350mV
200mV
N/A
RS
12
IN
a
RS=VREF
N/A
a. VREF is Input Reference Voltage.
LVDS mapping table select. See Fig7 to 8 and Table4 to 7.
MAP
VIHM
VILM
VIMM
Mapping Mode
Mapping MODE1
Mapping MODE2
Reserved
MAP
14
IN
IN
Pixel Data Mode.
MODE
MODE0
Mode
1
L
H
L
MODE1, MODE0
15, 16
L
L
Dual Link (Dual-in/Dual-out)
Dual Link (Single-in/Dual-out)
Single Link (Dual-in/Single-out)
Single Link (Single-in/Single-out)
H
H
H
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
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