THC63LVD103D _Rev.3.0_E
AC Timing Diagrams
LVDS Output
Vdiff = 0V
Vdiff = 0V
TCLK+/-
(Differential)
TA+/-
TB+/-
TC+/-
TA6 TA5 TA4 TA3 TA2 TA1 TA0
TB6 TB5 TB4 TB3 TB2 TB1 TB0
TC6 TC5 TC4 TC3 TC2 TC1 TC0
TD+/-
TE+/-
TD6 TD5 TD4 TD3 TD2 TD1 TD0
TE6 TE5 TE4 TE3 TE2 TE1 TE0
Previous Cycle
tTOP1
Next Cycle
tTOP0
tTOP6
tTOP5
tTOP4
tTOP3
tTOP2
Fig6. LVDS Output Data Position
Phase Lock Loop Set Time
/PDWN
2.0V
3.6V
3.0V
VCC
tTPLL
CLKIN
Vdiff = 0V
TCLK+/-
Fig7. PLL Lock Set Time
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THine Electronics, Inc.