PCF8563
CLKOUT output
A programmable square wave is available at the CLKOUT pin. Operation is controlled by
the CLKOUT frequency register (address 0DH). Frequencies of32.768 kHz (default), 1024,
32 and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a
charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and
enabled at power-on. If disabled it becomes high-impedance.
Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I 2 C-bus logic is initialized and all registers, including
the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC
and AE which are set to logic 1.
Voltage-low detection
Voltage-low detector and clock monitor
The PCF8563 has an on-chip voltage-low detector.
When V DD drops below Vlow the VL bit (Voltage
Low, bit 7 in the Seconds register) is set to
indicate that reliable clock/calendar information
is no longer guaranteed. The VL flag can only
be cleared by software.
The VL bit is intended to detect the situation
when V DD is decreasing slowly for example
under battery operation. Should V DD reach Vlow before power is re-asserted then the VL bit
will be set. This will indicate that the time may be corrupted.
Registers Organization
Table 1 registers overview
Bit positions labelled as ‘- ’are not implemented; those labelled with ‘0’ should always be
written with logic 0.
9/23
TGS [ Tiger Electronic Co.,Ltd ]
