PCF8563
C h a r a c t e r i s t i c s
SCL and SDA rise time
SCL and SDA fall time
Capacitive bus line load
Data set-up time
Symbol
tr
Test conditions
Min
Typ.
Max
0.3
Unit
µs
tf
0.3
µs
Cb
400
pF
ns
100
0
t SU;DAT
t HD;DAT
t SU;STO
Data hold time
Set-up time for STOP
condition
Tolerable spike width
on bus
ns
4.0
µs
µs
50
t SW
*1 Unspecified for f CLKOUT = 32.768 kHz.
*2 All timing values are valid within the operating supply voltage range at Tamb and
referenced to V IL and V IH with an input voltage swing of V SS to V DD
.
*3 I 2 C-bus access time between two STARTs or between a START and a STOP condition
to this device must be less than one second.
I2C-bus timing waveforms
6/23
TGS [ Tiger Electronic Co.,Ltd ]
