78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
LOOPBACK MODES
In SW mode, LLBK and RLBK bits in the Signal
Control register are provided to activate the local
and remote analog loopback modes respectively.
In HW mode, the LPBK pin can be used to activate
local and remote analog loopback paths as shown in
the table below.
In SW mode only, a Full Remote (digital) Loopback
bit FLBK is also available in the Advanced Tx
Control register. This loopback exercises the entire
Rx and Tx paths of the 78P2351 including the Tx
clock recovery unit. As such, the user must enable
either Serial Plesiochronous or Serial Loop-timing
transmit modes to utilize the Full Remote (digital)
Loopback.
EACH CHANNEL: Tx
Lock Detect
LPBK pin Loopback Mode
ECLxP/N
Tx CDR
TXxCKP/N
SIxDP/N
FIFO
CMI
Encoder
Low
Normal operation
Remote (analog) Loopback:
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PTOxCK
PMOD, SMOD[1:0], PAR
Recovered receive clock and data
looped back directly to the transmit
driver. The CMI decoder and most of
transmit path is bypassed (including the
redundant Tx monitor output)
RLBK
Float
SOxCKP/N
SOxDP/N
CMI
Decoder
Rx CDR
Adaptive
Eq.
RXxP/N
POx[3:0]D
POxCK
Lock Detect
LOS Detect
CMI
LLBK
EACH CHANNEL: Rx
Local (analog) Loopback:
Figure 9: Remote (Digital) Loopback
High
Transmit clock and data looped back to
receiver at the analog media interface.
INTERNAL POWER-ON RESET
Lock Detect
Power-On Reset (POR) function is provided on chip.
Roughly 50 µs after Vcc reaches 2.4V at power up,
a reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin. The PORB pin is a special function
analog pin that allows for the following:
ECLP/N
TXCKP/N
SIDP/N
Tx CDR
FIFO
CMI
Encoder
CMI2P/N
CMIP/N
SICKP/N
PICK
PI[3:0]D
PTOCK
PMOD, SMOD[1:0], PAR
RLBK,
RDSL
SOCKP/N
SODP/N
CMI
Rx CDR
Decoder
Adaptive
Eq.
RXP/N
PO[3:0]D
POCK
Lock Detect
LOS Detect
CMI
LLBK
•
•
•
Override the internal POR signal by driving in
Figure 7: Local (Analog) Loopback
an external active low reset signal;
Use the internally generated POR signal to
trigger other resets;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
Lock Detect
Tx CDR
ECLP/N
TXCKP/N
SIDP/N
FIFO
CMI
Encoder
CMI2P/N
CMIP/N
SICKP/N
PICK
NOTE: Do not pull-up the PORB pin to Vcc or drive
this pin high during power-up. This will prevent the
internal reset generator from resetting the entire chip
and may result in errors.
PI[3:0]D
PTOCK
PMOD, SMOD[1:0], PAR
RLBK,
RDSL
SOCKP/N
SODP/N
CMI
Rx CDR
Decoder
Adaptive
Eq.
RXP/N
PO[3:0]D
POCK
Lock Detect
LOS Detect
CMI
LLBK
Figure 8: Remote (Analog) Loopback
Page: 8 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
