78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
The frequency of this reference input is controlled by
the rate selection and the CKSL control pin or
register bit.
FUNCTIONAL DESCRIPTION
The 78P2351 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbps and 155.52Mbps line interfaces and
the digital universe. The chip is controllable through
pins or serial port register settings.
Reference Frequency
CKSL pin
SDO_E4 low
SDO_E4 high
Low
19.44MHz
77.76MHz
155.52MHz
E4 bit = 0
19.44MHz
77.76MHz
155.52MHz
17.408MHz
In hardware mode (pin control) the SPSL pin
must be low.
In software mode (SPSL pin high), control pins
are disabled and the 78P2351 must be
configured via the 4-wire serial port.
Float
N/A
High
139.264MHz
E4 bit = 1
17.408MHz
N/A
CKSL[1:0] bits
0 0
1 0
1 1
139.264MHz
MODE SELECTION
The SDO_E4 pin or E4 register bit determines which
rate the device operates in according to the table
below. This control combined with CKSL also
selects the reference clock frequency.
RECEIVER OPERATION
The receiver accepts serial data, at 155.52Mbps or
139.264Mbps from the RXP/N inputs. In CMI mode,
the input is differentially terminated with 75Ω and
transformer-coupled to a coaxial connector. In Fiber
(NRZ) mode, the input is differentially terminated
with 100Ω and AC-coupled to an optical transceiver
module. For board designs utilizing both coax and
fiber media options, an analog switch or mechanical
relay is required to switch between the different
terminations and media paths.
Rate
SDO_E4 pin
E4 bit
1
0
E4
High
STM-1, STS-3, OC-3 Low
The SEN_CMI pin or CMI register bit enables the
CMI encoder/decoder and selects one of two media
for reception and transmission: 75Ω coaxial cable in
CMI coding or optical fiber in Fiber (NRZ) mode.
The recovered CMI signal first enters an AGC and
anadaptive equalizer designed to overcome inter-
symbol interference caused by long cable lengths.
The variable gain differential amplifier automatically
controls the gain to maintain a constant voltage level
output regardless of the input voltage level. Note
that in Fiber (NRZ) mode, the input signals bypass
the adaptive equalizer.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a Delay Locked Loop (DLL), which
uses a reference frequency derived from the clock
applied to the CKREFP/N pins.
In serial mode, the clock and data are decoded and
transmitted through the LVPECL drivers. In parallel
mode, the data is decoded and converted into four
bit parallel segments before being transmitted
through the CMOS drivers. Note that in Fiber (NRZ)
mode, the CMI decoder is bypassed.
Media (coding)
75Ω Coax (CMI)
Fiber (NRZ)
SEN_CMI pin
High
CMI bit
1
0
Low
The SDI_PAR pin or PAR register bit selects the
interface to the framer to be 4-bit parallel CMOS or
serial LVPECL.
For each interface there are
different transmit timing modes available. See
TRANSMITTER OPERATION section for more info.
REFERENCE CLOCK
The 78P2351 requires a reference clock supplied to
the CKREFP/N pins. This reference clock is used
for clock recovery in the Rx DLL and Tx DLL. It is
also used for transmit re-timing in the synchronous
transmit modes.
Refer to the TRANSMITTER
OPERATION section for timing requirements during
synchronous (re-timing) transmit modes.
For reference frequencies of 77.76MHz or lower, the
device accepts a single ended CMOS clock at
CKREFP (with CKREFN grounded). For reference
frequencies of 139.264 or 155.52MHz, the device
accepts a differential LVPECL clock input at
CKREFP/N.
Receiver Monitor Mode
In CMI mode, the SCK_MON pin or MON register bit
enables the receiver’s monitor mode which adds
approximately 20dB of flat gain to the receive signal
before equalization. Rx Monitor Mode can handle
20dB of flat loss typical of monitoring points with up
to 6dB of cable loss. Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
Page: 4 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
