78P2351 Single Channel OC-3/STM1-E/E4 Line Interface Unit
Pulse Amplitude Adjustment
FUNCTIONAL DESCRIPTION (continued)
Controls for adjusting the transmit pulse amplitude
are provided in both hardware and software modes.
Amplitude boosts of 5% and 10% can be enabled by
the TXOUT0 pin or BST[1:0] register bits as follows:
Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4) or
38.88MHz (STM1) clock. These inputs are passed
to the 4x8 decoupling FIFO and then to a serializer
for transmission. For maximum compatibility, the
78P2351 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively. A
loop-timing mode is also available to allow external
remote loopbacks (i.e. line loopback in framer).
BST[1:0] bits
Amplitude
TXOUT0 pin
Low
Float
High
0 0
0 1
1 1
Normal
5% boost
10% boost
Transmit Monitor Mode
HW Control Pins SW Control Bits
Parallel
Mode
An optional redundant transmit output is available in
CMI mode for transmit monitoring. These outputs
(CMI2P/N) are activated when the RCSL pin or
RCSL register bit is activated.
SDI_PAR CKMODE
PAR
PMODE
Slave
High
High
Low
1
0
Slave +
CMI
Coax
Float
1
1
1
1
CMI2P/N
XFMR
*Loop-timing
CMI
Coax
CMIP/N
XFMR
Master
High
High
TDK
78P2351
CMI
Coax
*
Loop-timing in software mode requires SMOD[1:0]=11
RXP/N
XFMR
Reference
Clock
Figure 6: Transmit Monitor Output
CKREFP/N
PI[3:0]D
PIxCK
CMI
CMI
Coax
Coax
4-bit CMOS TTL
34/39 MHz
CMIP/N
RXP/N
XFMR
XFMR
Clock Synthesizer
Framer/
Mapper
TDK
78P2351
The transmit clock synthesizer is a low-jitter PLL that
generates a 278.528/311.04 MHz clock for the CMI
PO[3:0]D
POCK
4-bit CMOS TTL
34/39 MHz
encoder.
A synthesized 139.264/155.52 MHz
reference clock is also used in both the receive and
transmit sides for clock and data recovery.
Figure 4: Slave Parallel Mode
The 2x line rate clock is also available at the
TXCKxP/N pins for downstream synchronization or
interfacing to equipment lacking integrated clock
recovery.
Reference
Clock
CKREFP/N
PI[3:0]D
PTOCK
CMI
CMI
Coax
Coax
4-bit CMOS TTL
34/39 MHz
CMIP/N
RXP/N
XFMR
XFMR
Framer/
Mapper
TDK
Transmit Backplane Equalizer
78P2351
PO[3:0]D
POCK
4-bit CMOS TTL
34/39 MHz
An optional fixed equalizer is integrated in the
transmit path for architectures that use LIUs on
active interface cards. The fixed equalizer can
compensate for up to 1.5m of trace and can be
enabled by the TXOUT1 pin or TXEQ bit as follows:
Figure 5: Master Parallel Mode
TXEQ bit
Tx Equalizer
TXOUT1 pin
Low
Float
Transmit Driver
1
0
Enabled
Disabled
In CMI (electrical) mode, the CMIP/N pins connect
the chip to 75Ω coaxial cable through a transformer
and termination resistors. The transmitter converts
the data to CMI coding and shapes an analog signal
to meet the appropriate ITU-T G.703 template. The
CMI outputs are tri-stated during transmit disable
Transmit Loss of Lock
In serial modes using the integrated CDR, the
78P2351 will declare a loss of lock condition when
the recovered transmit clock frequency differs from
the reference clock by more than 100ppm in an
and
transmit
power-down
for
redundancy
applications.
interval greater than 420µs.
This condition is
When the CMI pin is low, the chip is in NRZ (optical)
mode. The output data signal from the ECLP/N pins
have LVPECL levels and interface directly to a fiber
module. The CMI driver, encoder and decoder are
disabled in NRZ (optical) mode.
cleared when the frequencies are less than
100ppm off for more than 500µs.
6
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