78P2351 Single Channel OC-3/STM1-E/E4 Line Interface Unit
If no serial transmit clock is available, as in Figure 2,
FUNCTIONAL DESCRIPTION (continued)
the 78P2351 can recover a clock from the serial
NRZ data input and pass the data through the FIFO.
In this mode, the NRZ transmit data should be
source synchronous with the reference clock applied
at CKREFP/N. The transmitter also includes a Loss
of Lock indicator (TXLOL) that can be used to trigger
an interrupt. Note that the FIFO is automatically re-
centered when the TXLOL register bit transitions
from high to low.
TRANSMITTER OPERATION
The transmitter section generates an analog signal
for transmission through either a transformer onto
the coaxial cable using CMI coding or directly to a
fiber optics module using NRZ coding.
The 78P2351 provides a flexible system interface for
compatibility with most off-the-shelf framers and
custom ASICs. The device supports a 4-bit parallel
interface in either slave or master clocking modes
and a number of serial NRZ timing modes.
System Reference Clock
CKREFP/N
Each of the serial NRZ transmit timing modes can be
configured in HW mode or SW mode as shown in
the table below.
NRZ
CMI
CMI
Coax
Coax
CMIP/N
RXP/N
SIDP/N
XFMR
XFMR
Framer/
Mapper
TDK
78P2351
NRZ
SOCKP/N
SODP/N
140 / 155 MHz
HW Control Pins SW Control Bits
Serial
Mode
SDI_PAR CKMODE PAR
SMOD[1:0]
Figure 2: Synchronous; data only
(Tx CDR enabled, FIFO enabled)
Synchronous
clock + data
Low
Low
0
0 0
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The FIFO allows long-term clock phase drift, not
exceeding +/- 25.6ns, to be handled without transmit
error. If the clock wander exceeds the specified
limits, the FIFO will over or under flow, and the
FERR register signal will be asserted. This signal
can be used to trigger an interrupt. This interrupt
event is cleared when an FRST pulse is applied, and
the FIFO is re-centered.
Synchronous
data only
Low
Low
n/a
Floating
High
0
0
X
1 0
0 1
11
Plesiochronou
s data only
n/a
Loop-timig
Synchronous Serial Modes
In Figure 1, serial NRZ transmit data is input to the
SIDP/N pins at LVPECL levels. By default, the data
is latched in on the rising edge of SICKP. A clock
decoupling FIFO is provided to decouple the on chip
and off chip clocks. The SICKP/N clock provided by
the framer/mapper IC must be source synchronous
with the internal reference transmit clock if the FIFO
is to be used.
Note: External remote loopbacks (i.e. loopback
within framer) are not possible in synchronous
operation (FIFO enabled) unless the reference
clock is synchronous with the recovered receive
clock (loop-timing).
System Reference Clock
Plesiochronous Serial Mode
CKREFP/N
Figure 3 represents the condition where no serial
transmit clock is available and the data is not source
synchronous to the reference clock input. In this
mode, the 78P2351 will recover a clock from the
serial plesiochronous data and bypass the FIFO.
Reference
NRZ
CMI
CMI
Coax
Coax
SIDP/N
CMIP/N
RXP/N
XFMR
XFMR
140 / 155 MHz
SICKP/N
Framer/
Mapper
TDK
78P2351
NRZ
SOCKP/N
SODP/N
140 / 155 MHz
Clock
XO
Figure 1: Synchronous; clock and data available
(Tx CDR bypassed, FIFO enabled)
CKREFP
NRZ
CMI
CMI
Coax
Coax
CMIP/N
RXP/N
SIDP/N
XFMR
XFMR
Framer/
Mapper
TDK
NRZ
78P2351
SOCKP/N
SODP/N
140 / 155 MHz
Figure 3: Plesiochronous; data only
(Tx CDR enabled, FIFO bypassed)
5
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