DS_6612_001
78M6612 Data Sheet
1.2 Analog Front End (AFE)
The AFE of the 78M6612 is comprised of an input multiplexer, a delta-sigma A/D converter and a voltage
reference.
1.2.1 Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB and VB of the
device. Additionally, using the alternate mux selection, it has the ability to select temperature and the
battery voltage. The multiplexer can be operated in two modes:
•
•
During a normal multiplexer cycle, the signals from the IA, IB, VA, and VB pins are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with the signal sources shown in Table 1. To prevent unnecessary drainage on the
battery, the battery monitor is enabled only with the BME bit (0x2020[6]) in the I/O RAM.
The alternate mux cycles are usually performed infrequently (e.g. every second) by the MPU. In order to
prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in the
ALT mux selections. Table 1 details the regular and alternative MUX sequences. Missing samples due
to an ALT multiplexer sequence are filled in by the CE.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Regular MUX Sequence
Mux State
ALT MUX Sequence
Mux State
EQU
0
1
2
3
0
1
2
3
2
IA
VA
IB
VB
TEMP
VA
IB
VBAT
In a typical application, IA and IB are connected to current sensors that sense the current on each branch
of the line voltage. VA and VB are typically connected to voltage sensors through resistor dividers.
The multiplexer control circuit handles the setting of the multiplexer. The function of the control circuit is
governed by the I/O RAM registers MUX_ALT, MUX_DIV and EQU. MUX_DIV controls the number of
samples per cycle. It can request 2, 3, or 4 multiplexer states per cycle. Multiplexer states above 4 are
reserved and must not be used. The multiplexer always starts at the beginning of its list and proceeds
until MUX_DIV states have been converted.
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle
and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT
will cause the multiplexer control circuit to wait until the next multiplexer cycle and implement a single
alternate cycle.
The multiplexer control circuit also controls the FIR filter initiation and the chopping of the ADC reference
voltage, VREF. The multiplexer control circuit is clocked by CK32, the 32768 Hz clock from the PLL
block, and launches with each new pass of the CE program.
1.2.2 A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 78M6612. The
resolution of the ADC is programmable using the FIR_LEN register as shown in Section 4.3 I/O RAM
Description. ADC resolution can be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1).
Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1.
In order to provide the maximum resolution, the ADC should be operated with FIR_LEN = 1.
Accuracy and timing specifications in this data sheet are based on FIR_LEN = 1.
Rev. 1.2
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
