DS_6612_001
78M6612 Data Sheet
Figures
Figure 1: IC Functional Block Diagram.....................................................................................................7
Figure 2: General Topology of a Chopped Amplifier ...............................................................................10
Figure 3: AFE Block Diagram ................................................................................................................11
Figure 4: Samples from Multiplexer Cycle ..............................................................................................14
Figure 5: Accumulation Interval..............................................................................................................15
Figure 6: Interrupt Structure...................................................................................................................39
Figure 7: Optical Interface......................................................................................................................42
Figure 8: Connecting an External Load to DIO Pins...............................................................................44
Figure 9: 3-Wire Interface. Write Command, HiZ=0 ..............................................................................47
Figure 10: 3-Wire Interface. Write Command, HiZ=1 ............................................................................48
Figure 11: 3-Wire Interface. Read Command........................................................................................48
Figure 12: 3-Wire Interface. Write Command when CNT=0 ..................................................................48
Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1 ................................................48
Figure 14: Functions Defined by V1.......................................................................................................49
Figure 15: Voltage. Current, Momentary and Accumulated Energy.......................................................51
Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers..................52
Figure 17: RTM Output Format..............................................................................................................52
Figure 18: Operation Modes State Diagram ...........................................................................................55
Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out) ...................................56
Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out).................................................57
Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out).............................................58
Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns.....................59
Figure 23: Power-Up Timing with V3P3SYS and VBAT Tied Together...................................................59
Figure 24: Power-Up Timing with VBAT Only.........................................................................................60
Figure 25: MPU/CE Data Flow...............................................................................................................61
Figure 26: MPU/CE Communication......................................................................................................62
Figure 27: Resistive Voltage Divider (Left), Current Transformer (Right).................................................63
Figure 28: Resistive Shunt.....................................................................................................................63
Figure 29: Crystal Frequency over Temperature.....................................................................................65
Figure 30: Crystal Compensation...........................................................................................................66
Figure 31: Connecting LCDs .................................................................................................................67
Figure 32: I2C EEPROM Connection .....................................................................................................70
Figure 33: 3-Wire EEPROM Connection................................................................................................70
Figure 34: Connections for the RX Pin...................................................................................................70
Figure 35: Connection for Optical Components......................................................................................71
Figure 36: Voltage Divider for V1 ...........................................................................................................72
Figure 37: External Components for RESET: Development Circuit (Left), Production Circuit (Right).......72
Figure 38: External Components for the Emulator Interface ...................................................................73
Figure 39: Wh Accuracy, 10 mA to 20 A at 120 V/60 Hz and Room Temperature Using a 4 mΩ
Current Shunt .....................................................................................................98
Figure 40: Measurement Accuracy over Harmonics at 240 V, 30A per IEC62053-2x Section 8.2.1
...........................................................................................................................98
Figure 41: Typical Measurement Accuracy over Temperature Relative to 25°C ......................................99
Figure 42: 64-Pin LQFP Pinout ...........................................................................................................100
Figure 43: 68-Pin QFN Pinout .............................................................................................................103
Rev. 1.2
5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
