73S8009R Data Sheet
DS_8009R_056
Table 1 describes the pin functions for the device.
Table 1: 73S8009R Pin Definitions
Pin
Name
Pin
Pin
Type
Description
(SO28) (QFN20)
Card Interface
I/O
25
24
23
15
NA
NA
IO
IO
IO
Card I/O: Data signal to/from card. Includes a pull-up
resistor to VCC.
AUX1
AUX2
AUX1: Auxiliary data signal to/from card. Includes a pull-up
resistor to VCC.
AUX2: Auxiliary data signal to/from card. Includes a pull-up
resistor to VCC.
RST
CLK
21
19
13
11
O
O
Card reset: provides reset signal to card.
Card clock: provides clock signal to card. The rate of this
clock is determined by the external clock frequency
provided on pin CLKIN.
PRES
PRES
VCC
26
16
22
20
16
10
14
NA
I
I
Card Presence switch: active high indicates card is present.
Should be tied to GND when not used, but includes a high-
impedance pull-down current source.
Card Presence switch: active low indicates card is present.
Should be tied to VDD when not used, but includes a high-
impedance pull-up current source.
PSO Card power supply – logically controlled by the sequencer,
output of LDO regulator. Requires an external filter
capacitor to GND.
GND
GND Card ground.
Miscellaneous Inputs and Outputs
CLKIN
TEST1
TEST2
NC
11
2
5
19
8
I
Clock source for the card clock.
–
–
–
This pin must be tied to GND in typical applications.
This pin must be tied to GND in typical applications.
Non-connected pin.
14
3,17,18
NA
Power Supply and Ground
VDD
28
17
System interface supply voltage and supply voltage for
internal circuitry.
VPC
GND
15
27
9
LDO regulator power supply source.
12
GND Ground.
Microcontroller Interface
CS
1
18
20
I
When CS = 1, the control and signal pins are configured
normally. When CS is set low, CMDVCC%, RSTIN, and
CMDVCC# are latched, IOUC, AUX1UC, and AUX2UC are
set to high-impedance pull-up mode and do not pass data
to or from the smart card. Signals RDY and OFF are
disabled to prevent a low output and the internal pull-up
resistors are disconnected.
OFF
4
O
Interrupt signal to the processor. Active low, multi-function
indicating fault conditions and card presence. Open drain
output configuration. It includes an internal 20 kΩ pull-up to
VDD. The pull-up is disabled in PWRDN and CS=0 modes.
6
Rev. 1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
