DS_8009C_025
73S8009C Data Sheet
Table 1 describes the pin functions for the device.
Table 1: 73S8009C Pin Definitions
Pin
Name
Pin
Pin
Equivalent
Circuit
Type
Description
(QFN32) (QFN20)
Card Interface
I/O
22
21
20
18
14
N/A
N/A
12
IO
IO
IO
O
Figure 17 Card I/O: Data signal to/from card. Includes a
pull-up resistor to VCC.
AUX1
AUX2
RST
Figure 17 AUX1: Auxiliary data signal to/from card.
Includes a pull-up resistor to VCC.
Figure 17 AUX2: Auxiliary data signal to/from card.
Includes a pull-up resistor to VCC.
Figure 16 Card reset: provides reset (RST) signal to card.
RST is the pass through signal on RSTIN.
Internal control logic will hold RST low when
card is not activated or VCC is too low.
CLK
PRES
PRES
VCC
16
14
13
19
17
10
8
O
Figure 15 Card clock: provides clock signal (CLK) to card.
CLK is the pass through of the signal on pin
CLKIN. Internal control logic will hold CLK low
when card is not activated or VCC is too low.
I
Figure 19 Card Presence switch: active high indicates
card is present. Should be tied to GND when
not used, but it Includes a high-impedance
pull-down current source.
N/A
13
11
I
Figure 19 Card Presence switch: active low indicates
card is present. Should be tied to VDD when
not used, but it Includes a high-impedance
pull-up current source.
PSO
Figure 14 Card power supply – logically controlled by
sequencer, output of LDO regulator.
Requires an external 0.47 µF low ESR filter
capacitor to GND.
GND
GND
–
Card ground.
Miscellaneous Inputs and Outputs
CLKIN
TEST1
7
6
7
I
Figure 19 Clock signal source for the card clock.
–
–
10
Factory test pin. This pin must be tied to
GND in typical applications
–
–
TEST2
30
20
Factory test pin. This pin must be tied to
GND in typical applications
Power Supply and Ground
VDD
29
19
PSO
Figure 14 System interface supply voltage and supply
voltage for companion controller circuitry.
Requires a minimum of two 0.1 µF capacitors
to ground for proper decoupling.
Rev. 1.4
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
