73S8009C Data Sheet
DS_8009C_025
FUNCTIONAL DIAGRAM
VBAT VBUS
VDD
CS
12
TEST1 TEST2
23
10 [7]
30 [20]
29 [19]
25
15 [9]
VP
vref
bias currents
VOLTAGE
REFERENCE
26 [16]
VPC
27 [17]
LIN
S2
S1
24 [15]
ON_OFF
VCC FAULT
VPC FAULT
VCC OK
4 [3]
CMDVCC5
VCC = 5
5 [4]
VCC = 3
17 [11]
SWITCH/LDO
REGULATOR
CMDVCC3
GND
CONTROL
LOGIC
19 [13]
32 [1]
OFF
POWER DOWN
ON/OFF
VCC
8
RDY
11
OFF_REQ
9
18 [12]
RESET
BUFFER
RST
OFF_ACK
16 [10]
CLOCK
BUFFER
CLK
RSTIN6 [5]
CLKIN 7 [6]
14 [8]
PRES
13
PRES
1.5MHz
R-C
OSC.
22 [14]
1 [2]
I/OUC
I/O
2
AUX1UC
3
21
SMART CARD I/O BUFFERS
AND SIGNAL LOGIC
AUX1
20
AUX2UC
AUX2
28 [18]
GND
Pin numbers reference to the QFN32 package
[Pin numbers] reference to the QFN20 package
Figure 1: 73S8009C Block Diagram
Rev. 1.4
3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
