73S1121F
EMV Smart-Card Terminal Controller
with Built-in Dual ISO-7816 Interface and USB
DATA SHEET
Pin
Total
Pins
Pin Name
Number
Type Description
128 TQFP
LCDDAT (3)
LCDDAT (2)
LCDDAT (1)
LCDDAT (0)
20
19
18
17
LCD driver dedicated I/O lines - Data pins.
Can be used as standard I/Os
4
I/O
LCD_Enable
LCD driver dedicated I/O line: LCD Enable. Can be used as standard
I/O
21
22
23
1
1
1
I/O
I/O
I/O
(LCDDAT (4))
LCD_RW
LCD driver dedicated I/O line: LCD Read/Write. Can be used as
(LCDDAT (5))
standard I/O
LCD_RS
LCD driver dedicated I/O line: LCD Register Select. Can be used as
standard I/O
(LCDDAT (6))
ANA_IN (5)
ANA_IN (4)
ANA_IN (3)
VREF
3
2
1
3
I
Analog Inputs - (Voltage detection inputs 0.2V to 2.5V ±3%)
128
1
1
1
O
O
I
Voltage reference. 2.5V ± 7%. Decouple with 0.1µF capacitor to VNA.
Bandgap output - internal use. To be decoupled with 0.1µF capacitor to
VBG
127
40
VNA. Nothing else should be connected to VBG
RESET
73S1121F Reset. Active high
Forces internal Flash programming in ISP mode at reset. Active High.
Inactive Low, suitable for normal operation. Internal pull-down allows NC
for normal operation
ISP_Program
38
1
I
7; 12; 43;
44; 89;
121; 122
N/C
5
2
1
-
-
I
Not Connected
Reserved
PROM_Program
To be connected to VND
Forces internal Flash programming in PROM parallel mode at reset.
Active High. Internal pull-down allows NC for normal operation
Digital security inputs that control the internal protection fuses. Active
High. Internal pull-down allows NC for normal operation
00 – Inactive.
120
SEC1
SEC2
4
5
01- Permanently deactivates both PROM programming mode,
TERIDIAN testing modes.
2
I
10 – Permanently deactivates the external interface of address and data
signals to the processor
11- Permanently deactivates the ISP programming mode.
Any combination of the 3 protection modes can be achieved by applying
the proper sequence on these pins
Page: 7 of 25
© 2005 TERIDIAN Semiconductor Corporation
Rev 2.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
