73S1121F
EMV Smart-Card Terminal Controller
with Built-in Dual ISO-7816 Interface and USB
DATA SHEET
Microcontroller
The 73S1121F core is an 8-bit 80C52 micro-controller, with embedded 5kB of RAM (data memory) and 64kB of
flash (program memory). An additional Information Block Flash cell (128B IFB) is available for storage of device
ID, serial number, firmware version etc
An embedded ROM boot-loader allows downloading of the flash memory (either program or IFB) through the
serial port. This programming mode can be forced externally (In-System-Programming = ISP mode) or also can
be called by the application (In-Application-Programming = IAP mode) through the Application Programming
Interface. The 73S1121F flash memory can also be programmed with a parallel PROM programmer. An interface
for external memory is provided to allow extension of the RAM up to 64kB total (addition of 59kB external).
Extension of the total program memory above the 64kB can be implemented by adding bank-switched external
memory pages, the firmware being responsible for management of the banks. Security fuses allows the user to
permanently disable, either the ISP mode, the PROM programming mode, the interface for external memory, or
any combination of the 3. It allows the 73S1121F, once programmed with an application, to run independently
without possibility from the external world to access the internal memory, or to re-download a non-authorized
application, or to run an external program.
The 73S1121F has a main oscillator that requires a 12MHz crystal. Internal clock circuitry generates clock signals
to the different blocks and to the CPU (that can be clocked at 6, 12 or 24MHz). An optional 2nd crystal (32,768Hz)
can be connected to a sub-system oscillator. It is associated with a 16-bit counter that can generate real-time
interrupts to the core, every 0.5s, 1s or 2s. The firmware application is then responsible to service this interrupt
and to update a real time/date counter for applications that require it. This sub-system clock can also be used as
a CPU clock for low-speed operation as an additional power saving mode. Keypad scanning can also operate
from a 1kHz clock generated from the sub-system clock.
The 73S1121F has the standard 8052 2-priority level interrupt structure, with 8 different interrupt sources: 2
external interrupts (pins INT2 and INT0), 3 timer interrupts, 1 serial/USB interrupt, 1 smart-card interrupt and a
shared interrupt (keypad, GPIO, RTC counter and analog comparator inputs).
The 73S1121F incorporates 3 timers, T0, T1 and T2 that can be clocked internally or externally by the respective
input signals on the pins USR0, USR1 and USR2.
Standard 8052 Power Down mode and IDLE mode are supported for power saving modes. The clock for each
block, as well as the analog circuitry (analog input, voltage reference and USB transceiver) and the DC-to-DC
converters (VCC generators for the card) can be independently enabled or disabled by firmware to optimize
power consumption.
Management of the embedded card interfaces, peripherals and communication capabilities are controlled by
means of dedicated registers in RAM. Management of the interrupts, of the power saving modes and of the clock
circuitry is also controlled through registers.
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© 2005 TERIDIAN Semiconductor Corporation
Rev 2.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
