DS_1903_032
73M1903 Data Sheet
Figures
Figure 1: SCLK and FS with SckMode = 0 ...................................................................................................7
Figure 2: Control Frame Position versus SPOS ...........................................................................................7
Figure 3: Serial Port Timing Diagram............................................................................................................9
Figure 4: Analog Block Diagram .................................................................................................................11
Figure 5: Clock Generation .........................................................................................................................17
Figure 6: Overall Receiver Frequency Response.......................................................................................19
Figure 7: Rx Passband Response ..............................................................................................................19
Figure 8: RXD Spectrum of 1 kHz Tone .....................................................................................................20
Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes .........20
Figure 10: Frequency Response of TX Path for DC to 4 kHz in Band Signal ............................................21
Figure 11: Serial Port Data Timing..............................................................................................................28
Figure 12: 32-Pin QFN Pinout.....................................................................................................................33
Figure 13: 20-Pin TSSOP Pinout................................................................................................................34
Figure 14: 32-Pin QFN Mechanical Specifications .....................................................................................35
Figure 15: 20-Pin TSSOP Mechanical Specifications.................................................................................36
Figure 15: NCO Block Diagram ..................................................................................................................41
Figure 16: PLL Block Diagram....................................................................................................................42
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles.........................................................4
Table 2: Memory Map ...................................................................................................................................8
Table 3: PLL Loop Filter Settings................................................................................................................11
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C......................................................................................13
Table 5: PLL Power Down ..........................................................................................................................14
Table 6: Examples of NCO Settings ...........................................................................................................14
Table 7: Clock Generation Register Settings for Fxtal = 27 MHz...............................................................15
Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz........................................................16
Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz..........................................................16
Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz......................................................17
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz........................................................17
Table 12: Receive Gain...............................................................................................................................18
Table 13: Peak to RMS Ratios for Various Modulation Types....................................................................23
Table 14: Serial I/F Timing..........................................................................................................................28
Table 15: Reference Voltage Specifications...............................................................................................29
Table 16: Maximum Transmit Levels..........................................................................................................29
Table 17: Receiver Performance Specifications.........................................................................................30
Table 18: Transmitter Performance Specifications.....................................................................................31
Table 19: 32-Pin QFN Pin Definitions.........................................................................................................33
Table 20: 20-Pin TSSOP Pin Definitions ....................................................................................................34
Rev. 2.0
3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
