73M1903C
Modem Analog Front End
DATA SHEET
PIN DESCRIPTION
The TERIDIAN 73M1903C modem Analog Front End (AFE) IC is available in a 32 pin QFN package. The
following table describes the function of each pin. There are three pairs of power supply pins, VPA
(analog), VPD (digital) and VPPLL (PLL). They should be separately decoupled from the supply source
in order to isolate digital noise from the analog circuits internal to the chip. VPPLL can be directly
connected to VPD. Failure to adequately isolate and decouple these supplies will compromise device
performance.
PIN NAME
TYPE
PIN #
DESCRIPTION
VND
VNA
GND
GND
PWR
PWR
PWR
1, 22
16
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
VPD
2, 25
9
VPA
Positive Analog Supply
VPPLL
20
Positive PLL Supply, shared with VPD
VNPLL
PWR
17
Negative PLL Ground
Master reset. When this pin is a logic 0 all registers are reset to their
default states; Weak-pulled high-default. A low pulse longer than 100ns
is needed to reset the device. The device will be ready within 100us after
this pin goes to logic 1 state.
RST
I
26
Crystal oscillator input. When providing an external clock source, drive
OSCIN.
OSCIN
I
19
18
OSCOUT
GPIO(0-7)
O
I/O
Crystal oscillator circuit output pin.
3, 4, 5, 6, 23 24,
30, 31
Software definable digital input/output pins.
RXAN
RXAP
I
14
15
10
11
12
13
Receive analog negative input.
Receive analog positive input.
Transmit analog negative output 1
Transmit analog negative output 2
Transmit analog positive output 1
Transmit analog positive output 2
I
TXAN1
TXAN2
TXAP1
TXAP2
O
O
O
O
Serial interface clock. With master mode and SCLK continuous selected,
Freq = 256*Fs ( =2.4576MHz for Fs=9.6kHz). For slave mode, this pin
must be pulled down by a resistor (<4.7kΩ).
SCLK
I/O
8
SDOUT
SDIN
FS
O
I
32
29
7
Serial data output (or input to the host).
Serial data input (or output from the host)
O
Frame synchronization. (Active Low)
Type of frame sync. 0 = late (mode0); 1 = early (mode1). Weak-pulled
high – default
TYPE
I
27
Controls the SCLK behavior after FS. Open, weak-pulled high = SCLK
Continuous; tied low = 32 clocks per R/W cycle.
Delayed frame sync to support daisy chain mode with additional
73M1903C devices
SckMode
I
28
21
FSD
O
Table 1: 32 QFN Pin Description
Page: 4 of 46
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
