73M1903C
Modem Analog Front End
DATA SHEET
for each FS. The SDOUT and FS pins change values following a rising edge of SCLK. The SDIN pin is
sampled on the falling edge of SCLK. Figure 3 shows the timing diagrams for the serial port.
32 Cycles of SCLK
SCLK
FS
(early mode)
SCLK Relative to early FS
32 Cycles of SCLK
SCLK
FS
(late mode)
SCLK Relative to late FS
Figure 1: SCLK and FS with SckMode=0
DATA FRAMES
SPOS = 0
SPOS = 1
CONTROL FRAMES
Figure 2: Control frame position vs. SPOS
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© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3