73M1903
Modem Analog Front End
DATA SHEET
New to TERIDIAN 73M1903 modem AFE IC is a feature that shuts off the serial clock (SCLK) after 32
cycles of SCLK following the frame synch (Figure 2). This mode is controlled by the SckMode pin. If this
pin is left open the clock will run continuously. If SckMode is low the clock will be gated on for 32 clocks
for each FS. The SDOUT and FS pins change values following a rising edge of SCLK. The SDIN pin is
sampled on the falling edge of SCLK. Figure 4 shows the timing diagrams for the serial port.
32 Cycles of sclk
SCLK
FS(mode1)
SCLK and FS in mode 1
32 Cycles of sclk
SCLK
FS(mode0)
SCLK and FS in mode 0
Figure 1 -SCLK and FS with SckMode = 0
Figure 2 -Control frame position vs. SPOS
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© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
