73M1903
Modem Analog Front End
DATA SHEET
SIGNAL DESCRIPTION
The TERIDIAN 73M1903 modem AFE IC is available in a 32 pin TQFP or QFN package with same pin
out. The following table describes the function of each pin. There are two pairs of power supply pins,
VPA(analog) and VPD(digital). They should be separately decoupled from the supply source in order to
isolate digital noise from the analog circuits internal to the chip. Failure to adequately isolate and
decouple these supplies will compromise device performance.
PIN NAME
TYPE PIN #
DESCRIPTION
VND
GND
GND
PWR
PWR
PWR
PWR
1,22
16
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
VNA
VPD
2,25
10
VPA
Positive Analog Supply
VPPLL
VNPLL
20
Positive PLL Supply, shared with VPD
Negative PLL Ground
17
Master reset. When this pin is a logic 0 all registers are reset to
their default states; Weak-pulled high- default
RST
I
9
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
OSCIN
I
19
18
OSCOUT
GPIO(0-7)
O
I/O
Crystal oscillator circuit output pin.
3, 4, 5, 6,
Software definable digital input/output pins.
23, 24,30,31
VREF
RXAP
RXAN
TXAP
TXAN
O
I
13
15
14
12
11
Reference voltage pin (Reflects Vref)
Receive analog positive input.
I
Receive analog negative input.
O
O
Transmit analog positive output
Transmit analog negative output
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576MHz for Fs=9.6kHz)
Serial data output (or input to the host).
Serial data input (or output from the host)
SCLK
O
8
SDOUT
SDIN
O
I
32
29
FS
O
I
7
Frame synchronization. (Active Low)
Type of frame sync. Open, weak-pulled high = early (mode1);
tied low = late (mode0)
TYPE
27
Controls the SCLK behavior after FS. Open, weak-pulled high
= SCLK Continuous; tied low = 32 clocks per R/W cycle.
SckMode
I
28
Table 1: -32 TQFP and QFN Pin Description
Page: 5 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
